1. Field
The present invention relates to the field of integrated circuits and packaging and, in particular, to metal trace and feature formation processes and structures.
2. Description of Related Art
As the electronic arts have moved to smaller and lighter weight devices, it has become increasingly important that integrated circuits and integrated circuit packages process greater numbers of signals and provide for greater density of signal routing features such as signal traces and bias traces associated with substrates used in both integrated circuits and integrated circuit packages. As a result, it is desirable to minimize the width of signal and bias traces and place as many signal traces as possible on a given substrate. However, this means electrical properties, such as impedance and shielding provided by the bias traces must be more accurately controlled.
Currently used substrates typically include a substrate first surface and a substrate second surface, opposite the substrate first surface with a substrate body, or thickness, between the two surfaces. Currently used substrates also typically include bias traces, such as ground and/or power and/or voltage potential traces, and signal traces, such as input/output (I/O), or data, signal traces formed on one of the substrate surfaces, such as the substrate first surface, as well as a bias plane, such as a ground and/or power and/or voltage potential plane, attached to the opposite substrate surface, such as the substrate second surface. As a result, an electric field between the bias traces, the signal traces, and the bias plane has a generally vertical orientation and the electrical properties provided by the bias traces, such as impedance control and shielding, are provided in vertically offset planes of bias traces and signal traces, typically offset by the thickness of the substrate.
What is needed is a method and apparatus that allows for greater accuracy and control of the electrical properties provided by bias traces.